1. Field of the Invention
The invention generally relates to the powering of circuit blocks and devices in a system implemented as an integrated circuit, system on a chip or a chip on board using the wasted power from low swing, high speed differential driver supply.
2. Prior Art
A typical data processing and transmitting system 100 is shown in FIG. 1. The system shows a typical system on chip (SOC) implementation of data processing circuits with differential drivers, their peripheral circuits 110, and a set of associated circuit blocks 105. The associated circuits 105 include integrated circuits like memory, digital-to-analog converter (DAC), analog-to-digital converter (ADC), clock circuits, and other circuits that make up the SOC 100. It also shows a termination load circuit 120 that is either part of the SOC 100 or part of the remote receiver. The twin differential drivers NL0 and NL1 of the source transmitter 115, driving the signal lines TXN and TXP respectively, are connected through the resistors R0 and R1 to power supply (Removed receiver side) 120. The resistors are connected typically in circuit shown in the example, to the 3.3V nominal power supply. The transmitter drivers draw current from the receiver power supply, through the resistors that enable the signal swing as per the system specification. Since the drivers are differential they draw a constant DC current and consume power. Part of the power that is consumed is in the switching of the differential drivers, and the rest is used for setting up the DC conditions of the drivers with a fixed voltage and/or current. This part of the power is wasted power.
In the prior art FIG. 1 the power supply to the circuits like pre-amplifier 111, phase locked-loop (PLL) 112, data processing circuits 113, bias circuits 114, and associated circuits 105 are provided from the power connection to the SOC 100 from an external supply.
A typical driver 115 of a high speed transmission channel draws about 10.0 to 24.0 mA nominal DC current from the power supply. Typically the signal swing across the load resistors 120 is 0.4 to 0.6 V which leaves 2.7 V out of the typical 3.3V supply. This power is currently dissipated in setting up the DC conditions of the drivers and hence wasted. This power is available and can be tapped to power part of the peripheral circuits 111, 112 and 114 of the driver, data processing circuits 113 and some of the associated circuits 105 in the SOC 100 as disclosed in this disclosure.
It would be therefore advantageous to provide a circuit that reduces the amount of wasted power. It would be further advantageous if such a circuit can reduce the power consumption of the system and enable a low power implementation.